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ACS710
120 kHz Bandwidth, High Voltage Isolation
Current Sensor with Integrated Overcurrent Detection
Functional Block Diagram
Latching Version
VCC
D
CLK
Q
FAULT_EN
VOC
Hall
Bias
POR
POR
FAULT Reset
–
R
Fault Latch
Drain
FAULT
+
2V REF
Control
IP+
Sensitivity
Trim
OC Fault
Fault
Comparator
–
+
Logic
3 mA
VZCR
IP–
Hall
Amplifier
Signal
Recovery
GND
R F(INT)
FILTER
V OUT(Q)
Trim
VIOUT
Terminal List Table, Latching Version
Number
1 through 4
Name
IP+
Description
Sensed current copper conduction path pins. Terminals for current being sensed;
fused internally, loop to IP– pins; unidirectional or bidirectional current flow.
Pin-out Diagram
5 through 8
9
IP–
GND
Sensed current copper conduction path pins. Terminals for current being sensed;
fused internally, loop to IP+ pins; unidirectional or bidirectional current flow.
Device ground connection.
IP+ 1
IP+ 2
IP+ 3
IP+ 4
IP– 5
IP– 6
IP– 7
IP– 8
16 FAULT_EN
15 VOC
14 VCC
13 FAULT
12 VIOUT
11 FILTER
10 VZCR
9 GND
10
11
12
13
14
15
VZCR
FILTER
VIOUT
ˉFˉ ˉA ˉUˉˉLˉ ˉTˉ
VCC
VOC
Voltage Reference Output pin. Zero current (0 A) reference; output voltage on this
pin scales with V CC . (Not a highly accurate reference.)
Filter pin. Terminal for an external capacitor connected from this pin to GND to set
the device bandwidth.
Analog Output pin. Output voltage on this pin is proportional to current flowing
through the loop between the IP+ pins and IP– pins.
Overcurrent Fault pin. When current flowing between IP+ pins and IP– pins
exceeds the overcurrent fault threshold, this pin transitions to a logic low state.
Supply voltage.
Overcurrent Input pin. Analog input voltage on this pin sets the overcurrent fault
threshold.
16
FAULT_EN Enables overcurrent faulting when high. Resets ˉFˉ ˉA ˉUˉˉLˉ ˉTˉ when low.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
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